Integrated System Labratory

            Tahereh Kahookar Toosi, Mohammad Hossein Maghami, Farzad Inanlou, and Reza Lotfi

Design methodologies and related algorithms and computer-aided design (CAD) software tools for high-performance analog and mixed-signal circuits are of increasing importance. These tools not only reduce the time-to-market parameter of the projects but also improve the quality and optimality of analog and mixed-signal IC designs (e.g. power reduction, but also avoiding expensive redesign runs). The first goal of the project is “Developing a CAD tool for high-performance operational amplifiers”. Based on a simulation-equation method, a CAD tool for power-optimized design of low-voltage high-gain high-speed opamps in deep-sub-micron processes has been developed.

Equation-based methods usually suffer from lack of accuracy since they don’t consider higher-order effects but they can usually find the globally optimal solution very fast. On the other hand, simulation-based methods use more complicated circuit models to improve accuracy but they can only find locally optimal circuits. In the proposed CAD, utilizing an automatic interface between MATLAB as analytical tool and HSPICE as simulation tool, first the metrics-optimized equations are solved by MATLAB and circuit sizing is performed. Then, based on the achieved sizes, the input file is provided for HSPICE and it is called to simulate the circuit. The simulation results are then read from HSPICE output file. According to a comparison between the achieved metrics and desired specifications, the initial assumptions and equations are corrected and new circuit sizing is performed. This procedure continues until the desired metrics are obtained. Thus the proposed CAD tool gains the benefits of equation-based approaches and that of the simulation-based methods, while avoiding their shortcomings.

     Using the proposed CAD, two low-voltage low-power cascode-compensated two-stage opamps with high-gain, high-bandwidth and short settling time are designed for front-end SHA and first gain-stage of an 11-bit 40 MS/s pipelined ADC in 0.18um process with supply voltage of 1.8V. The current results of this research were submitted as a paper entitled “ISECAD: An Iterative Simulation-Equation-based Opamp-Design CAD Tool” to International Symposium on Circuits And Systems (ISCAS), Island of Kos, Greece, May 2006, and one for ICEE’06.