Integrated System Labratory

Mohammad Reza Nabavi, Ehsan Zhian Tabasy, Hassan Sarbishaei and Reza Lotfi

            Pipelining is the best approach to implement high-speed, medium-to-high-resolution analog-to-digital converters (ADCs). In a pipelined ADC with high signal-to-noise ratio (SNR) the values of the stage resolutions, the stage capacitors and the compensation capacitors of the operational amplifiers all affect the noise power and also the power consumption of the ADC. In this project we’ve proposed a novel design methodology to determine the optimum values of all these parameters simultaneously in order to minimize the power consumption while the noise requirement is satisfied.

The methodology is examined in both switched-capacitor and switched-opamp structures. We’ve designed a 1-V 12-bit 10MS/s switched-opamp ADC as well as a 1.2-V 12-bit 40MS/s switched-capacitor ADC. Simulations have been done using the models of a 0.18-um CMOS process with MIM caps. The main challenging parts of such designs are low-voltage fast-and-accurate-settling opamps, very-low-voltage highly-linear switches and low-voltage comparators.

One paper has been extracted from the project about a 1-V 12-bit SO ADC, accepted to be presented in MidWest Symposium on Circuits and Systems 2005, MWSCAS’05. A paper entitled “Power Optimization in Low-Voltage High-Speed High-Resolution Pipelined ADCs,” and another “A 1-V 12-Bit Switched-Opamp Pipelined ADC with Power Optimization” have been submitted to International Symposium on Circuits And Systems (ISCAS), Island of Kos, Greece, May 2006 and two other papers for 14^th Iranian Conf. on Electrical Engineering, ICEE’2006. Besides, a paper about a new structure for positive-feedback operational amplifiers was presented in MWSCAS’05.