Digital Circuit Design
Homeworks
  • Homework #1 , deadline 4shanbeh 20/7/90
  • Homework #2
  • Homework #3
  • Homework #4
  • Homework #5
  • Exercise answers and Exams
  • Final Exams
  • New Exams
  • Quick Verilog Sequential Circuiits
  • Final Project Description - Deadline 12 Bahman
  • ActiveHDL Class : shanbeh 8/11/90 Sa'at 17:30-19:30 Class#123
  • Sessions on solving homework problems will be held by Mr Farajzadeh every wednesday from 12:00 to 14:00 in Class #123
  • OBSOLETE Homework VHDL , deadline seshanbeh 6/11/88
  • OBSOLETE Sample VHDL work files
  • Laboratory Instructions #3

    • Midterm Examination

    • Time : Hour 16 to 18, Tuesday, 8 Azar, 1390
    • Place : Class "will be notified later"

    Resources